Hot Pages: Software Caching for Raw Microprocessors

This paper describes Hot Pages, a software based solution for managing on-chip data on the MIT Raw Machine, a scalable, parallel, microprocessor architecture. This software system transparently manages the mapping between the program address space and available on-chip memory. Hot Pages implements a multi-bank memory structure, allowing multiple references in parallel, to provide memory bandwidth matched to the computational resources on the Raw microprocessor. Because virtualization is handled in software rather than hardware, the system is easier to design and test, and provides flexibility for customized solutions. The challenge for this kind of software based approach is to balance the tradeoffs between the added software overheads against opportunities provided by a memory management scheme specialized for each application. Our technique, called Hot Pages, combines both compile-time and runtime techniques to reduce the software overheads. The Hot Pages system optimizes the translation code for the hit case and caches translated virtual page descriptions likely to be reused for nearby memory references. We use pointer analysis to identify program memory references that can reuse a translated virtual page description. This allows us to specialize the code for each memory reference, reducing the cost of performing translations, and eliminating it entirely in some cases. The framework also provides additional opportunities for optimization because the cost of sophisticated memory management schemes can be relegated to translation misses. We present simulation results for a variety of applications running with Hot Pages on a prototype Raw system.